超大规模集成电路中低功耗设计与分析

AbstractAbstractLiu Hainan (Microelectronics and Solid-State Electronics)Directed by Professor Zhou YumeiAs the design of IC go into larger and faster,the issue about power consumptionis more critical.It is necessary to analysis the power accurately and manage lowpower techniques in every step of the design flow,so as to assure the efficient,reliableand correct function.Choosing the appropriate low power solutions depends on careful power analysisas well as understanding the capabilities of available tools.Analyzing powerrequirements as early as possible in the design flow helps avoid power relateddisasters.Early analysis also makes power goals easier to attain because higher-leveltechniques save the greatest amount of power.The thesis is made up of two main parts based on the discussion of the digitalCMOS power consumption.First of all,this thesis introduces and demonstrates a top-down VLSI designmethodology for power analysis,discuss the method to estimate the power on RTLand gate level,which could serve as a guide to the floorplan and place route.Andestimate the power consumption about a 4.5 million VLSI on several level,drawsome conclusion from comparing the test result of the fabricated chip.In the second,completed a low power technique on the structure level.DynamicVoltage Scaling is a technique using the lowest level voltage in real time on differentblock dramatically reducing energy consumption,while maintaining the desired levelof performance,which has a nice prospect to realize low power.The thesis hasdeveloped a DVS circuit,which could get the corresponding lowest voltage accordingto the system frequency.Take a 16X16 multiplier as a test circuit to simulate together,proving the low power action of DVS.Keyword:low power,power analysis,Dynamic Voltage Scaling